TE entries 345 preferably have the Stop bit set on the first entry of any new read/write command and for non-read/write commands. Preferably, TE entries 345 without a Data, Stat, DRel, SRel or Stop bit set are defined as null entries and are simply fetched and then deleted. 345 stored in staging registers 405, 410 is checked by DMA 225 to determine what will be done with that TE entry 345. TE entry 345 is valid if one of the following bits is set: Stop, Status or Status Release (SRel). The Status context is not used, and the Status and SRel bits are cleared in TE entries 345. DMA 225 will retrieve data TE entries 345 and will load DXFER register 370 with the transfer length so the DBR (data block release) pulses are counted if the active host context is the same as the disk context. A Status Go bit denotes that status retrieval channel 360 is enabled to retrieve status TE entries 345 from TE entry list 350 in buffer memory. When both data and status TE entries 345 are staged, DMA 225 normally executes all TE entries 345 in the retrieval channel 380 until list 350 runs out of data (read) or space (write)

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