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Read transfers operate with the normal buffer thresholds to control reconnection. The status control bit is normally not needed for reads since good status is always sent after the read data. As the disk transfer fills up the buffer, the first command's data transfer will complete and good status will be sent immediately afterward. The microprocessor could also create a fake TE which re-programmed the data context as a disk context with the remaining DXFER length. Still, DMA 225 may not be able to continuously transfer the entire transfer length because the transfer rate between the buffer memory and the host is much greater than the transfer rate between the buffer memory and the disk. If the microprocessor changes the disk context, it preferably first clears the GO bit. The active context registers are read-only, and the inactive context registers can be read/written by the microprocessor or loaded/stored from/to a context frame in buffer memory. DMA 225 can toggle between the active and inactive context frames, allowing very fast swaps in situations where the next context frame needed has been anticipated and loaded to the inactive registers. When the queue becomes empty, the GO bit will remain set so that additional sequential reads can be queued without microprocessor intervention